As digital data processing technology continues to improve, the need for higher data transmission rates continues to increase. For example, the IEEE long-reach multi-mode fiber standard IEEE 802.3aq (sometimes referred to as 10 GBASE-LRM) provides for a channel bit rate greater than 10 Gbit/s. Achieving data rates above a few gigabits per second is very challenging due to performance limitations of silicon-based integrated circuits.
During a typical high speed data communication, a sending device transmits symbols at a fixed and known symbol rate via a channel. A receiving device detects the sequence of symbols in order to reconstruct the transmitted data. A “symbol” is a state or significant condition of the channel that persists for a fixed period of time, called a “symbol interval.” A symbol may be, for example, an electrical voltage or current level, an optical power level, a phase value, or a particular frequency or wavelength. A change from one significant channel condition to another is called a symbol transition. Each symbol may represent (i.e., encode) one or more binary bits of the data. Alternatively, the data may be represented by symbol transitions, or by a sequence of two or more symbols. The simplest digital communication links use only one bit per symbol; a binary ‘0’ is represented by one symbol (e.g., an electrical voltage or current signal within a first range), and binary ‘1’ by another symbol (e.g., an electrical voltage or current signal within a second range).
When a symbol is transmitted via a non-ideal physical medium (e.g., a fiber optic cable or insulated copper wires), dispersion by the medium may result in a portion of the energy of the symbol being located outside of the symbol interval in which the symbol was transmitted. When the energy outside the symbol interval perturbs symbol energy in neighboring symbol intervals, the symbol becomes a source of intersymbol interference (ISI).
In order to compensate for signal distortions due to ISI, equalization circuits have been added to digital data receiver circuits. Unlike linear equalizers, the nonlinear decision feedback equalizer (DFE) is advantageously capable of reducing the effects of ISI without amplifying noise or crosstalk, and hence it would be a desirable equalization option in high data rate systems.
As the name suggests, a DFE employs a feedback path, which generates an error signal based on previously-decided data symbols. In a straightforward implementation, a number of cascaded circuit elements are employed to generate the error signal and add it to the received input signal, a process that must be implemented in less than one symbol interval to avoid falling behind. At 10 Gbit/s (1010 bits/sec), the symbol interval is 100 picoseconds, a value that is unachievable by cascaded circuit elements implemented with currently available silicon semiconductor processing technologies.